\doxysubsubsubsection{UARTEx TXFIFO threshold level }
\hypertarget{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level}{}\label{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level}\index{UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}}


UART TXFIFO threshold level.  


\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_gac0167b844b8cc2d183b55a0b296b2803}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+8}}~0x00000000U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga7b6a3451b4d3677ba49f05228832edad}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+4}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3cc91bacf5659188d4ef8d13fc48b5c3}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+0}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga3ded7de796281c47106eab832068534d}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+2}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4651a05997c8bef8485185f7c8874142}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+1}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga0dd7780c824caddd1476cb59b9d5e5d0}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+3\+\_\+4}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3cc91bacf5659188d4ef8d13fc48b5c3}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+0}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4651a05997c8bef8485185f7c8874142}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+1}})
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga8e36c5786a037adae9a124a3094fc374}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+7\+\_\+8}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa2683f01784119560144bd0c7fd8d85e}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+2}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga302d541c0419d26567cc0da09486e73d}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+8\+\_\+8}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa2683f01784119560144bd0c7fd8d85e}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+2}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3cc91bacf5659188d4ef8d13fc48b5c3}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+0}})
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
UART TXFIFO threshold level. 



\label{doc-define-members}
\Hypertarget{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga3ded7de796281c47106eab832068534d}\index{UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}!UART\_TXFIFO\_THRESHOLD\_1\_2@{UART\_TXFIFO\_THRESHOLD\_1\_2}}
\index{UART\_TXFIFO\_THRESHOLD\_1\_2@{UART\_TXFIFO\_THRESHOLD\_1\_2}!UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_TXFIFO\_THRESHOLD\_1\_2}{UART\_TXFIFO\_THRESHOLD\_1\_2}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga3ded7de796281c47106eab832068534d} 
\#define UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+2~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4651a05997c8bef8485185f7c8874142}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+1}}}

TX FIFO reaches 1/2 of its depth \Hypertarget{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga7b6a3451b4d3677ba49f05228832edad}\index{UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}!UART\_TXFIFO\_THRESHOLD\_1\_4@{UART\_TXFIFO\_THRESHOLD\_1\_4}}
\index{UART\_TXFIFO\_THRESHOLD\_1\_4@{UART\_TXFIFO\_THRESHOLD\_1\_4}!UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_TXFIFO\_THRESHOLD\_1\_4}{UART\_TXFIFO\_THRESHOLD\_1\_4}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga7b6a3451b4d3677ba49f05228832edad} 
\#define UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+4~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3cc91bacf5659188d4ef8d13fc48b5c3}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+0}}}

TX FIFO reaches 1/4 of its depth \Hypertarget{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_gac0167b844b8cc2d183b55a0b296b2803}\index{UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}!UART\_TXFIFO\_THRESHOLD\_1\_8@{UART\_TXFIFO\_THRESHOLD\_1\_8}}
\index{UART\_TXFIFO\_THRESHOLD\_1\_8@{UART\_TXFIFO\_THRESHOLD\_1\_8}!UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_TXFIFO\_THRESHOLD\_1\_8}{UART\_TXFIFO\_THRESHOLD\_1\_8}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_gac0167b844b8cc2d183b55a0b296b2803} 
\#define UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+8~0x00000000U}

TX FIFO reaches 1/8 of its depth \Hypertarget{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga0dd7780c824caddd1476cb59b9d5e5d0}\index{UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}!UART\_TXFIFO\_THRESHOLD\_3\_4@{UART\_TXFIFO\_THRESHOLD\_3\_4}}
\index{UART\_TXFIFO\_THRESHOLD\_3\_4@{UART\_TXFIFO\_THRESHOLD\_3\_4}!UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_TXFIFO\_THRESHOLD\_3\_4}{UART\_TXFIFO\_THRESHOLD\_3\_4}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga0dd7780c824caddd1476cb59b9d5e5d0} 
\#define UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+3\+\_\+4~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3cc91bacf5659188d4ef8d13fc48b5c3}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+0}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4651a05997c8bef8485185f7c8874142}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+1}})}

TX FIFO reaches 3/4 of its depth \Hypertarget{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga8e36c5786a037adae9a124a3094fc374}\index{UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}!UART\_TXFIFO\_THRESHOLD\_7\_8@{UART\_TXFIFO\_THRESHOLD\_7\_8}}
\index{UART\_TXFIFO\_THRESHOLD\_7\_8@{UART\_TXFIFO\_THRESHOLD\_7\_8}!UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_TXFIFO\_THRESHOLD\_7\_8}{UART\_TXFIFO\_THRESHOLD\_7\_8}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga8e36c5786a037adae9a124a3094fc374} 
\#define UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+7\+\_\+8~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa2683f01784119560144bd0c7fd8d85e}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+2}}}

TX FIFO reaches 7/8 of its depth \Hypertarget{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga302d541c0419d26567cc0da09486e73d}\index{UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}!UART\_TXFIFO\_THRESHOLD\_8\_8@{UART\_TXFIFO\_THRESHOLD\_8\_8}}
\index{UART\_TXFIFO\_THRESHOLD\_8\_8@{UART\_TXFIFO\_THRESHOLD\_8\_8}!UARTEx TXFIFO threshold level@{UARTEx TXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_TXFIFO\_THRESHOLD\_8\_8}{UART\_TXFIFO\_THRESHOLD\_8\_8}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga302d541c0419d26567cc0da09486e73d} 
\#define UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+8\+\_\+8~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa2683f01784119560144bd0c7fd8d85e}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+2}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3cc91bacf5659188d4ef8d13fc48b5c3}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+0}})}

TX FIFO becomes empty 